// +FHDR------------------------------------------------------------
//                 Copyright (c) 2022 .
//                       ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename      : w_interface.sv
// Author        : 
// Created On    : 2022-08-25 15:10
// Last Modified : 
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------

`ifndef __W_INTERFACE_SV__
`define __W_INTERFACE_SV__

`timescale 1ns/1ps

interface w_interface(input clk, rst_n);

	logic 	        valid;
	logic		    ready;

    logic [32 -1:0] data;
    logic [16 -1:0] addr;

	clocking drv @(posedge clk);
		default input #1ps output #1ps;
		output	valid;
		input   ready;
        output data;
        output addr;
	endclocking : drv
	modport pkt_drv (clocking drv);

	clocking mon @(posedge clk);
		default input #1ps output #1ps;
		input	valid;
		input   ready;
        input data;
        input addr;
	endclocking : mon
	modport pkt_mon (clocking mon);

	clocking ready_drv @(posedge clk);
		default input #1ps output #1ps;
		input	valid;
		output  ready;
        input data;
        input addr;
	endclocking : ready_drv
	modport pkt_ready_drv (clocking ready_drv);

endinterface

`endif
